How do FPGAs implement the inequality operator?

From curiosity and to understand the cost of the operator I often using in FPGA design.

Let's assume I am doing the following equation in Verilog:

OUT = A[15:0] >= B[15:0];

How will the FPGA implement this operator? Will it just use a LUT? I don't understand how a LUT solves this logic.

More specifically if relevant I am using Quartus and Stratix10 FPGA.

This is what the RTL Viewer shows:

This is what the Technology Map Viewer shows:

I would like to understand how it is actually fitted into a Stratix10 logic cell:

What I understand:

I can see that in the technology viewer it is using 4 or 5 primitives with 4 inputs to calculate the inequality - meaning it's probably using 2 logic cells.

I can't imagine what the logic inside the LUT looks like.